1. Field of the Invention
The invention relates to a power circuit to be employed for an integrated circuit chip, and more particularly to a power circuit ensuring stable operation for an integrated circuit chip having a plurality of operation frequency modes.
2. Description of the Related Art
A power circuit to be employed for an integrated circuit chip has been designed to be able to suppress an oscillation of a power source voltage caused by resonant oscillation to thereby prevent malfunction in the integrated circuit chip to which power is provided from a power source through the power circuit.
FIG. 1 illustrates one of conventional power circuits. An integrated circuit chip 2201 includes an output buffer 2202 and a clock driver 2203 both of which drive a great load. The output buffer 2202 and the clock driver 2203 are connected to both a power line 2204 and a ground line 2205. Between a power source VDD and a ground GND of the integrated circuit chip 2201, there exist parasitic inductors (L) 2206 and 2207, parasitic resistors (R) 2208, 2209, 2210, 2211, 2212 and 2213, and parasitic capacitors (C) 2214, 2215, 2216 and 2217. The integrated circuit chip 2201 is designed to have an operation frequency and higher harmonics which are not in accord with a resonance point of an RLC circuit defined by the above-mentioned parasitic elements R, L and C in a power supply line. In addition, the resistors 2212 and 2213 are connected in series to the on-chip decoupling capacitors 2214 to thereby suppress a gain, which ensures a stable operation of the power circuit.
For instance, Japanese Unexamined Patent Publication No. 5-28759 published on Feb. 5, 1993 has suggested a semiconductor integrated circuit including a voltage drop circuit. The semiconductor integrated circuit is designed to have a resistance against a surge voltage applied to a Vcc pin, and include a circuit including a capacitance and a resistance connected in series to each other, between a Vcc wiring and a Vss wiring in the semiconductor integrated circuit chip, in order to suppress noises caused by fluctuation in a power source current. The capacitance positioned between the Vcc and Vss wirings delays a surge voltage applied to the Vcc pin from propagating to an internal circuit, and increases an area of PN junction connected to the Vcc wiring to thereby increase an amount of a current passing therethrough. As a result, it is possible to enhance a resistance against a surge voltage applied to the Vcc pin. The capacitance also lowers a resonance frequency defined by an inductance in a power supply line located outside the semiconductor integrated chip and a capacitance in a power supply line located inside the semiconductor integrated chip, and as a result, a great fluctuation in a power current is relaxed.
Japanese Unexamined Patent Publication No. 5-55461 published on Mar. 5, 1993 has suggested a semiconductor integrated circuit. According to this Publication, there is a problem that since a capacitor C for absorbing noises thereinto and an inductance of a lead forms a LC circuit together, when a LC resonance frequency is greater than an operation frequency of the integrated circuit by k-th times wherein k is a positive integer, an oscillation in a power voltage caused by a noise current is made higher, resulting in a malfunction of the integrated circuit. The integrated circuit is designed to include a resistor having a resistance R and connected in series to the capacitor C. The resistance R is defined as follows. EQU 0.219.times.(L/C).sup.1/2 .ltoreq.R&lt;0.431(L/C).sup.1/2
Japanese Unexamined Patent Publication No. 6-188323 published on Jul. 8, 1994 has suggested a semiconductor integrated circuit device package, wherein a package is made an electrically conductive material and formed with a recess, and a resistive chip acting as a resistor to a power source is positioned in an extension of a wiring layer so that the resistive chip does not constitute a parallel resonance circuit.
Japanese Unexamined Patent Publication No. 60-74467 published on Apr. 26, 1985 has suggested a power circuit including a resistive element in a power supply line for preventing resonance. According to this Publication, the suggested power circuit makes it possible to suppress an oscillation as small as possible, which is secondarily generated when an output buffer in MOS integrated circuit is operated at a high rate, and is caused by resonance defined by capacitances located between a power source and a ground and inductances in a power supply line located outside the MOS integrated circuit, without deteriorating an operation speed of the output buffer of the MOS integrated circuit.
Japanese Unexamined Patent Publication No. 57-149763 published on Sep. 16, 1982 has suggested an integrated circuit including an impedance between a power source and a load in which a significant fluctuation in a current is generated. The impedance relaxes a fluctuation in a current in a power source terminal, caused by the significant fluctuation in a current in the load.
Japanese Unexamined Patent Publication No. 4-130659 published on May 1, 1992 has suggested a semiconductor integrated circuit including a transistor for precharging between bus lines and a higher level power supply line, and a transistor for discharging between bus lines and a lower level power supply line. The suggested semiconductor integrated circuit makes it possible to suppress a rate of change in a gate voltage in the transistor for discharging to thereby avoid GND voltage from raising.
Japanese Unexamined Patent Publication No. 6-102946 published on Apr. 15, 1994 has suggested a power circuit where a constant voltage is kept applied thereto, even if a fluctuation in a voltage is generated due to an instantaneous fluctuation in a current in the power circuit.
The above-mentioned conventional circuits have problems as follows.
The first problem is that a resistor additionally connected in series to an on-chip decoupling capacitance for preventing resonance degrades an original function of the on-chip decoupling capacitance. The reason is as follows. When charges are to be supplied through a decoupling capacitance for compensating for a voltage drop caused by switching, charges are supplied also through a resistor. Hence, if the resistor has a great resistance, charges are incompletely supplied.
The second problem is that it is quite difficult to put a resonance frequency out of an operation frequency range when an operation frequency is in a wide range, even if a power source is designed in such a manner that a resonance point is not accord with an operation frequency. This is because it would be necessary to significantly vary parasitic elements for putting a resonance point out of a wide frequency band, which is accompanied with a problem that a large area has to be prepared for arrangement of a circuit to vary parasitic elements.